The present invention relates to an input-output circuit cell and a semiconductor integrated circuit apparatus.
In a semiconductor integrated circuit apparatus such as a one-chip CPU, or the like, not only a logical device unit and a memory unit but also an external interface unit for interface connection to the outside and an input-output circuit unit serving as a buffer between the external interface unit and an input-output terminal of the outside are formed on one semiconductor chip.
The input-output terminal of an input-output circuit constituting an input-output circuit unit is connected to an input-output bump by means of wiring in a multilayer wiring substrate. Generally, the pitch interval of input-output bumps is made equal to the pitch interval of pins formed in a package. On the other hand, the size of an input-output circuit is determined on the basis of load drive force for driving circuit species or external devices and in accordance with the available semiconductor process, so that the pitch interval of input-output circuits is different from the pitch interval of input-output bumps. Accordingly, when input-output circuits are to be arranged on a semiconductor chip, it is necessary to match the pitch interval of the input-output circuits with the pitch interval of the input-output bumps (that is, the pitch interval of pins in the package). Assuming now that the pitch interval of pins in the package (that is, the pitch interval of the input-output bumps) is 300 xcexcm and the pitch interval of the input-output circuits is 180 xcexcm, then the least common multiple of the two is calculated and input-output bumps and input-output circuits are arranged collectively in design of layout so that six input-output circuits are made to correspond to six pins (six input-output bumps) in the package in a distance of 1800 xcexcm.
As described above, in the semiconductor integrated circuit apparatus, input-output circuits cannot be arranged arbitrarily on the semiconductor chip because the pins of the package and the input-output circuits are designed to be arranged collectively in design of layout.
Further, because the pins of the package and the input-output circuits must be arranged collectively in design of layout, the input-output circuits are arranged, for example, at the periphery of the semiconductor chip, that is, at four corners of the square semiconductor chip. In the system having input-output circuits arranged at the periphery of the semiconductor chip, an external interface unit must be, however, arranged near the center of the semiconductor chip so that the distances from the input-output circuits arranged at the four corners are kept equal. As a result, with the advance of the increase of the chip size, the distances between the external interface unit and the input-output circuits increase, so that propagation delay increases. Particularly when the semiconductor integrated circuit apparatus is applied to a high-performance CPU, overhead on performance increases. Further, in the system having input-output circuits mounted at the periphery of the semiconductor chip, the number of input-output bumps allowed to be arranged in one side is limited on the basis of the size of the semiconductor chip and the pitch interval of the input-output bumps. That is, the number of input-output terminals is limited.
With the advance of the integration of LSIs on the basis of the recent semiconductor refining technique, a central processing unit (CPU), and so on, are integrated into one chip and the number of input-output terminals required for one chip is showing a tendency to increase. Accordingly, in the system having input-output circuits mounted at the periphery of the semiconductor chip, the number of input-output terminals is limited to the order of hundreds of terminals.
On the contrary, as another method for arranging pins of the package and input-output circuits collectively in design of layout, for example, there is known a method in which input-output circuits are arranged in the form of stripes in the inside of the semiconductor chip. If eight input-output circuits are arranged in the form of stripes in the inside of the semiconductor chip, the number of input-output terminals can be doubled compared with the system having input-output circuits arranged at four corners of the semiconductor chip. By the arrangement of input-output circuits in the form of stripes in the inside of the semiconductor chip, the distances between the external interface unit disposed at the center of the semiconductor chip and the input-output circuits can be relatively reduced compared with the aforementioned system. Accordingly, propagation delay can be reduced. In the system having input-output circuits arranged in the form of stripes in the inside of the semiconductor chip, however, a logic unit is separated by the input-output circuits arranged in the form of stripes. As a result, overhead on internal logic propagation delay increases because internal logic is required to propagate over the input-output circuits. Furthermore, there has been a U.S. Pat. No. 5,341,049 as a related art.
An object of the present invention is to provide an input-output circuit cell by which input-output circuits can be arranged arbitrarily on a semiconductor chip.
Another object of the present invention is to provide a semiconductor integrated circuit apparatus in which propagation delay between an external interface unit and input-output circuits is small, so that overhead on internal logic propagation delay is small.
In order to achieve the above objects, according to an aspect of the present invention, provided is an input-output circuit cell comprising: an input-output circuit formed on a semiconductor chip and including a signal terminal, and an electric source terminal; and a plurality of input-output bumps connected to the signal and electric source terminals of the input-output circuit through wirings, wherein the plurality of input-output bumps are made to correspond to the input-output circuit and the input-output bumps are arranged at a center in a planes of projection of the input-output circuit. With such a configuration, input-output circuits can be arranged arbitrarily on a semiconductor chip.
In order to achieve the above objects, according to another aspect of the present invention, provided is an input-output circuit cell comprising: an input-output circuit formed on a semiconductor chip and including a signal terminal, and an electric source terminal; and a plurality of input-output bumps connected to the signal terminal and the electric source terminal of the input-output circuit through wirings respectively, wherein the plurality of input-output bumps are made to correspond to the input-output circuit, and the input-output bumps are arranged relative to the input-output circuit so that an area occupied by the plurality of input-output bumps is equal to an area occupied by the input-output circuit. With such a configuration, input-output circuits can be arranged arbitrarily on a semiconductor chip.
In order to achieve the above objects, according to a further aspect of the present invention, provided is a semiconductor integrated circuit apparatus comprising an input-output circuit unit formed on a semiconductor chip so as to be connected to an external interface unit, wherein: the input-output circuit unit includes a plurality of input-output circuit cells; each of the input-output circuit cells includes an input-output circuit having a signal terminal and an electric source terminal, and a plurality of input-output bumps connected to the signal and electric source terminals of the input-output circuit through wirings; and layout is made on the semiconductor chip with each input-output circuit cell, as a unit, having the plurality of input-output bumps made to correspond to the input-output circuit. With such a configuration, input-output circuits can be arranged arbitrarily on a semiconductor chip.
In the above semiconductor integrated circuit apparatus, preferably, the input-output circuit unit is disposed on two adjacent sides of the semiconductor chip so as to be L-shaped. In such a configuration, propagation delay between the external interface unit and the input-output circuits can be reduced to thereby reduce overhead on internal logic propagation delay.